1. Field of the Invention
The present invention generally relates to the art of microelectronic integrated circuits, and more specifically to a process for fabricating a semiconductor device including an antireflective etch stop layer.
2. Description of the Related Art
A semiconductor integrated circuit includes a large number of individual transistors and other microelectronic devices which must be interconnected to provide the desired functionality. A variety of interconnection techniques have been developed in the art.
Tungsten damascene is a process which includes forming an insulator layer of, for example, silicon dioxide over the microelectronic devices of an integrated circuit. A photoresist layer is formed over the insulator layer, and exposed and developed using photolithography to form a mask having holes therethrough in areas corresponding to desired interconnects.
The insulator layer is etched through the holes in the mask using Reactive Ion Etching (RIE) to form corresponding holes through the insulator layer down to interconnect areas (source, drain, metallization, etc.) of the devices. The holes are filled with tungsten which ohmically contacts the interconnect areas to form local interconnects, self-aligned contacts, vertical interconnects (vias), etc.
Etching of the insulator layer is conventionally performed using octafluorobutene (C.sub.4 F.sub.8) etchant, which also has a high etch rate for silicon. For this reason, a mechanism must be provided to perform this etch without allowing the etchant to act on the silicon of underlying interconnect areas.
Such a mechanism includes forming an etch stop layer of, for example, silicon nitride or silicon oxynitride underneath the insulator layer, and performing the etch in two stages. The first stage is the octafluorobutene etch through the insulator layer, which terminates at the etch stop layer since octafluorobutene has a relatively low etch rate for the etch stop layer. Then, a second RIE etch is performed using fluoromethane (CH.sub.3 F), which forms holes through the portions of the etch stop layer that are exposed through the holes in the insulator layer, down to the interconnect areas of the devices. This is possible because fluoromethane has a high etch rate for the etch stop layer, but a low etch rate for silicon dioxide.
The structure can be further facilitated by using a silicide technique to increase the conductivity of the interconnect areas of the devices. Siliciding is a fabrication technique that enables electrical interconnections to be made that have reduced resistance and capacitance.
The silicide process comprises forming a layer of a refractory metal silicide material such as tungsten, titanium, tantalum, molybdenum, etc. on a silicon interconnect area (source or drain diffusion region) or on a polysilicon gate to which ohmic contact is to be made, and then reacting the silicide material with the underlaying silicon material to form a silicide surface layer having much lower resistance than heavily doped silicon or polysilicon. A silicide surface layer formed on a polysilicon gate is called "polycide", whereas a silicide surface layer formed on silicon using a self-aligned process is called "salicide".
A problem which has remained unsolved in the fabrication of semiconductor integrated circuits using reactive ion etching and a conventional etch stop layer is relatively low selectively. This refers to the rate at which the etch stop layer is etched relative to the rate at which the overlying silicon dioxide insulator layer is etched. Conventional etch stop materials have relatively low selectivities, on the order of 8:1, which make it difficult to accurately end the etching process.
If the octafluorobutene etching is stopped too soon, the silicon dioxide insulator layer will not be etched through completely. In this regard, it is generally necessary to perform overetching in order to ensure the formation of a vertical hole wall through the insulator material. If the etching is stopped too late, the etch stop layer can be etched through and a portion of the underlying silicon layer damaged by undesired etching.